The invention relates to a test pattern generator circuit for IC testing equipment.
A testing equipment for a semiconductor integrated circuit (hereafter simply referred to as IC) includes a test pattern generator which generates a test pattern and an expected value pattern, applies the test pattern to an IC, which is a device under test (DUT), the response of which is compared against the expected value pattern to determine if if they are equal, and a result of such determination is saved in a memory. In a conventional test pattern generator circuit, the number of bits generated for the test pattern per tester channel remains constant. Accordingly, if it is desired to generate a variety of waveforms and corresponding expected value patterns or to achieve a test at a high rate, there has been a need to use a "pin multiplex" or to increase the number of bits per tester channel.
The term "pin multiplex" refers to the function of connecting two tester channel data to one pin of a device under test (DUT) in order to generate a more complicated test waveform or to perform a test at a high rate. FIG. 3 shows an odd-numbered and an even-numbered channel testing circuit CH(2i+1), CH(2i+2) which are adjacent to each other among a plurality of channel testing circuits. As shown, an odd-numbered channel testing circuit CH(2i+1) and an even-numbered channel testing circuit CH(2i+2), which are adjacent to each other, are normally used in combination. Each channel testing circuit CH includes a pattern memory 2 which stores test patterns and expected value patterns. The pattern memory 2 in each channel stores data for one mega-words where one word comprises three bits, for example.
In a normal mode which does not implement "pin multiplex", a mode signal MUX is set to "0" to disable an AND gate 13 and to cause a selector 14 to select an input to its B terminal to be delivered to its output. As shown at row B in FIG. 4, the pattern memory 2 of a respective channel delivers eight word data W1-W8 or a total of twenty-four bits in parallel, which are then converted in a parallel/serial conversion circuit 3 into a stream of parallel-by-bit and serial-by-word data W1-W8, as illustrated at row C in FIG. 4, for input to a formatter 4. The combination of the pattern memory 2 and the parallel/serial conversion circuit 3 forms a test pattern generator circuit 20. A rate signal RATE, as shown at row A in FIG. 4, is applied to a terminal 1 from a rate signal generator 10, and a timing generator circuit 5 generates timing data which is referenced to the timing of the rate signal and which is used in the formatter 4 to produce test waveforms V1-V8 (see row D in FIG. 4) and expected value data E1-E8 for eight cycles. The test waveform is applied, is with a delay of one test cycle, to one of input/output pins, Pm, of DUT 9 through an OR gate 6, a driver 7 and an input/output terminal 8 while the expected value data is applied to a digital compare circuit 11.
A response waveform which is delivered from the DUT 9 to the input/output pin Pm is input through the input/output terminal 8 to a comparator 15 where it is compared against a reference level to determine its digital value, which is then fed to the digital compare circuit 11 to be compared against the expected value data from the formatter 4. If the occurrence of a disagreement (fail) is found, it is recorded in a fail data memory 12.
During the pin multiplex mode, the mode signal MUX is set to "1", whereby the AND gate 13 is disabled and the selector 14 selects an input to its A terminal or an output from the comparator 15 of an odd-numbered channel.
In the pin multiplex mode, the parallel/serial conversion circuit 3 of an odd-numbered channel testing circuit CH(2i+1) delivers each of serial data W1-W8 during a first half of a corresponding test cycle, as shown at row C in FIG. 5. On the other hand, the parallel/serial conversion circuit 3 of an even-numbered channel testing circuit CH(2i+2) delivers each of serial data W1'-W8' during a second half of a corresponding test cycle, as shown at row F in FIG. 5. Outputs W1-W8 and W1'-W8' from the parallel/serial conversion circuits 3 of the respective channels are input to respective formatters 4 where test waveforms V1-V8 and V1'-V8' are produced on the basis of the timing data, for example, with a delay of one test cycle, and are fed to the OR gates 6 of the odd-numbered channels to be applied to the input/output pins Pm through the drivers.
It is to be noted that in the pin multiplex mode, the input/output terminals 8' of the even-numbered channels are not connected to any input/output pin of DUT 9.
The connection of a hardware for two channels with a single pin on the DUT in this manner enables a complicated test waveform to be produced. Also, the application of an odd-numbered channel test waveform during a first half of one test period and of an even-numbered channel test waveform during a second half of the test period, both to a common pin Pm, enables a testing operation to be performed at a frequency higher than the fundamental tester frequency or a higher rate test.
An alternative approach to the pin multiplex operation comprises increasing the number of bits per word generated by the test pattern generator circuit, from normal three bits to four or five bits per word.
It is recognized that the pin multiplex technique which has been employed heretofore in order to achieve a variety of test waveforms/expected values or a higher rate test exhibits a disadvantage that the number of effective channels of the tester is reduced because two channels of the tester resource are used for one pin of DUT. It may be inappropriate depending on the number of pins on a device and the channel arrangement of the tester.
In addition, the conventional approach of increasing the number of bits for one word/pin which defines the test waveform for one test cycle from the test pattern generator circuit requires an increased memory capacity, causing a cost increase of the tester. Furthermore, where the generation of simple waveforms expected values or a low rate of operation is sufficient for purpose of the test, which is applicable in most instances, the increase in the number of bits is nothing more than the redundancy, wastefully increasing the demand on the user.